Shashwat Shrivastava

My work focuses on FPGA compilation and architecture–compiler co-design. I develop compilation techniques that adapt to emerging application requirements and evolving FPGA architectures, enabling FPGA-based solutions with higher performance, lower area, and improved energy efficiency. I am interested in reconfigurable computing, domain-specific architectures, and efficient compilation tools for emerging applications. I completed my Ph.D. from EPFL, advised by Prof. Babak Falsafi and Dr. Mirjana Stojilović.

I completed my B.Tech. (Bachelor of Technology) + M.S. (Master of Science) by research in Electronics and Communication Engineering at International Institute of Information Technology, Hyderabad through a dual degree program. For my Master's thesis, under the guidance of Prof. Suresh Purini, I developed an FPGA-based hardware accelerator for stereo vision applications.

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