Shashwat Shrivastava

Shashwat Shrivastava

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I am a Ph.D. student at EPFL, advised by Dr. Mirjana Stojilović. I am broadly interested in FPGA architecture and Computer-Aided Design. My research is focused on reducing the compile time for FPGAs by incorporating architectural enhancements and rethinking CAD algorithms.

I completed my B.Tech. (Bachelor of Technology) + M.S. (Master of Science) by research in Electronics and Communication Engineering at International Institute of Information Technology, Hyderabad through a dual degree program. For my Master's thesis, under the guidance of Prof. Suresh Purini, I developed an FPGA-based hardware accelerator for stereo vision applications.

Besides academia, I am an ardent cricket fan and a skilled player. I am interested in theories of human origin and behavioral studies of humans from the perspective of psychology.


ICCAD 2023
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck [pdf] Shashwat Shrivastava, Stefan Nikolić, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilović
HaSS 2023
Instruction-level Power Side-channel Leakage Evaluation of Soft-core CPUs on Shared FPGAs [pdf] Ognjen Glamočanin, Shashwat Shrivastava, Jinwei Yao, Nour Ardo, Mathias Payer, Mirjana Stojilović
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism [pdf] Ziaul Choudhury, Shashwat Shrivastava, Lavanya Ramapantulu, Suresh Purini
FPL 2020
FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation [pdf] Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini
FPL 2020
Accelerating Local Laplacian Filters on FPGAs [pdf] Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini


Ph.D. in Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland.
B.Tech. in Electronics and Communications Engineering + M.S. by research International Institute of Information Technology - Hyderabad (IIIT-H), India

Professional Experience

Jun, 2023 - Dec, 2023
AMD, Research Intern in the FPGA architecture team
Jan, 2021 - July, 2021
Intel Labs, Research Intern at Processor Architecture Lab (PAR)
May, 2019 - Aug, 2019
Google Summer of Code (GSoC), Student Developer for RoboComp
May, 2018 - July, 2018
Bluespec, Intern